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CY7C1041DV33
4-Mbit (256K x 16) Static RAM
Features
* Pin- and function-compatible with CY7C1041CV33 * High speed -- tAA =10 ns * Low active power -- ICC = 90 mA @ 10 ns (Industrial) * Low CMOS standby power * * * * * -- ISB2 = 10 mA 2.0 V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in lead-free 48-ball VFBGA, 44-lead (400-mil) Molded SOJ and 44-pin TSOP II packages
Functional Description[1]
The CY7C1041DV33 is a high-performance CMOS Static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0-I/O7), is written into the location specified on the address pins (A0-A17). If Byte HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8-I/O15) is written into the location specified on the address pins (A0-A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 - I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0-I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
256K x 16
COLUMN DECODER
A9 A10 A 11 A 12 A 13 A14 A15 A16 A17
BHE WE CE OE BLE
Note 1. For guidelines on SRAM system design, please refer to the "System Design Guidelines" Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05473 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 17, 2006
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CY7C1041DV33
Selection Guide
-10 (Industrial) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 90 10 -12 (Automotive)[2] 12 95 15 Unit ns mA mA
Pin Configurations
48-ball Mini FBGA
(Top View) 1 BLE I/O0 I/O1 VSS VCC I/O6 I/O7 NC 2 OE BHE I/O 2 I/O3 I/O 4 I/O 5 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O 10 I/O 11 I/O12 6 NC I/O 8 I/O9 VCC VSS A B C D E F G H
A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SOJ
TSOP II Top View
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
I/O13 I/O14 WE A11 I/O15 NC
A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10
Note 2. Automotive product information is Preliminary.
Document #: 38-05473 Rev. *D
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CY7C1041DV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND
[3]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Industrial Automotive Ambient Temperature -40C to +85C -40C to +125C VCC 3.3V 0.3V 3.3V 0.3V Speed 10 ns 12 ns
.... -0.3V to +4.6V
DC Voltage Applied to Outputs in High-Z State[3] .....................................-0.3V to VCC +0.3V DC Input Voltage[3] ..................................-0.3V to VCC +0.3V
DC Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH
[3]
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
-10 (Industrial) Min. 2.4 0.4 2.0 -0.3 -1 -1 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 Max.
-12 (Automotive) Min. 2.4 0.4 2.0 -0.3 -1 -1 VCC + 0.3 0.8 +1 +1 95 85 75 25 Max.
Unit V V V V A A mA mA mA mA mA
VIL[3] IIX IOZ ICC
Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC 100MHz 83MHz 66MHz 40MHz
ISB1
Automatic CE Power-down Current--TTL Inputs
Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE Max. VCC, Power-down CE > VCC - 0.3V, Current--CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
10
15
mA
Note 3. Minimum voltage is-2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
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CY7C1041DV33
Capacitance[4]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Thermal Resistance[4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board FBGA Package 27.89 14.74 SOJ Package 57.91 36.73 TSOP II Package 50.66 17.17 Unit C/W C/W
AC Test Loads and Waveforms[5]
10 ns device
OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Rise Time: 1 V/ns (a) High-Z Characteristics R 317 3.3V OUTPUT 5 pF R2 351 (c) (b) Fall Time: 1 V/ns 30 pF* Z = 50 ALL INPUT PULSES 90% GND 10% 90% 10%
3.0V
Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
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CY7C1041DV33
AC Switching Characteristics Over the Operating Range[6]
Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z CE HIGH to
[8, 9]
Description
-10 (Industrial) Min. 100 10 10 3 10 5 0 5 3 5 0 10 5 0 6 Max.
-12 (Automotive) Min. 100 12 12 3 12 6 0 6 3 6 0 12 6 0 6 Max.
Unit
s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Low-Z[9] High-Z[8, 9] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE,tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device.
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CY7C1041DV33
AC Switching Characteristics Over the Operating Range[6](continued)
Parameter Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[8, 9] 7 Byte Enable to End of Write 10 7 7 0 0 7 5 0 3 5 8 12 8 8 0 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns ns Description -10 (Industrial) Min. Max. -12 (Automotive) Min. Max. Unit
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Ind'l Auto 0 tRC Conditions[12] Min. 2.0 10 15 Max. Unit V mA mA ns ns
tCDR[4] tR[13]
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Notes 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. No input may exceed VCC + 0.3V. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s
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CY7C1041DV33
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
DATA OUT
HIGH IMPEDANCE
Notes 14. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW.
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CY7C1041DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
Notes 17. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1041DV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[17, 18]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE
BHE, BLE t DATA I/O NOTE 19 t
HZOE SD
tHD
DATAIN VALID
Note 19. During this period the I/Os are in the output state and input signals should not be applied.
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CY7C1041DV33
Switching Waveforms (continued)
Write Cycle No. 4 (WE Controlled, OE LOW)
BHE, BLE ADDRESS
tWC
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O NOTE 19 tLZWE tSD tHD
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1041DV33-10BVI CY7C1041DV33-10BVXI CY7C1041DV33-10VXI CY7C1041DV33-10ZSXI 51-85082 51-85087 Package Diagram 51-85150 48-ball VFBGA 48-ball VFBGA (Pb-Free) 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II (Pb-Free) Package Type Operating Range Industrial
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CY7C1041DV33
Ordering Information
Speed (ns) 12 Ordering Code CY7C1041DV33-12BVXE CY7C1041DV33-12VXE CY7C1041DV33-12ZSXE Package Diagram 51-85150 51-85082 51-85087 Package Type 48-ball VFBGA (Pb-Free) 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II (Pb-Free) Operating Range Automotive
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
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CY7C1041DV33
Package Diagrams(continued)
Figure 2. 44-lead (400-mil) Molded SOJ (51-85082)
51-85082-*B
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CY7C1041DV33
Package Diagrams(continued)
Figure 3. 44-pin TSOP II (51-85087)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1041DV33
Document History Page
Document Title: CY7C1041DV33 4-Mbit (256K x 16) Static RAM Document Number: 38-05473 REV. ** *A *B ECN NO. 201560 233729 351117 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF PCI Description of Change Advance Data sheet for C9 IPP 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the `Ordering information' Changed from Advance to Preliminary Removed 15 and 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind'l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in Note# 2 Changed Note# 4 on AC Test Loads Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Data Retention Characteristics/Waveform and footnote # 11, 12 Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 and from 44-lead (400-mil) Molded SOJ V34 to 44-lead (400-mil) Molded SOJ V44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns Product Information Added Lead-Free Ordering Information Shaded Ordering Information Table Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Included Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Updated the ordering information and replaced Package Name column with Package Diagram in the Ordering Information Table Added -10BVI product ordering code in the Ordering Information table
*C
446328
See ECN
NXR
*D
480177
See ECN
VKN
Document #: 38-05473 Rev. *D
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